The present application claims the benefit of and priority to provisional application Ser. No. 61/782,460, filed on Mar. 14, 2013, and entitled “Semiconductor Packages Utilizing Leadframe Panels with Grooves in Connecting Bars.” The present application is also a continuation-in-part of application Ser. No. 13/662,244 filed on Oct. 26, 2012, and entitled “Compact Wirebonded Power Quad Flat No-Lead (PQFN) Package,” which in turn claims priority to application Ser. No. 13/034,519 filed on Feb. 24, 2011, and entitled “Multi-Chip Module (MCM) Power Quad Flat No-Lead (PQFN) Semiconductor Package Utilizing a Leadframe for Electrical Interconnections,” which in turn claims priority to provisional application Ser. No. 61/459,527 filed on Dec. 13, 2010, and entitled “Low Cost Leadframe Based High Power Density Full Bridge Power Device.” The present application claims the benefit of and priority to all of the above-identified applications. Moreover, the disclosure and contents of all of the above-identified applications are hereby incorporated fully by reference into the present application.
Fabricating a leadframe-based semiconductor package can include utilizing a leadframe panel, which includes several leadframe modules that are connected by bars of the leadframe panel. The leadframe modules are singulated into semiconductor packages by sawing through the bars of the leadframe panel that connect the leadframe modules. Sawing through the bars of the leadframe panel can leave excess conductive material, such as burrs. The excess conductive material may interfere with testing of a semiconductor package by preventing the semiconductor package from properly making contact with test probes. Furthermore, the excess conductive material may result in the shorting of leads of the semiconductor package.